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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2011. all rights reserved all other trademarks mentioned are the property of their respective owners. 6-channel led driver with ultra low dimming capability isl97672a the isl97672a is an integrated power led driver that controls six channels of led current for lcd backlight applications. the isl97672a is capable of driving leds from 4.5v to 26.5v, with a maximum output of 45v. the isl97672a employs an adaptive boost switching architecture that allows direct pwm dimming with linearity as low as 0.007% at 200hz or 0.8% at 20khz. dimming can be as high as 30khz. the isl97672a can compensate for non-uniformity of forward voltage drops in the led strings. its headroom control circuit monitors the highest led forwar d voltage string for output regulation to minimize voltage headroom and power loss in a typical multi-string operation. typical current matching between channels is 0.7%. the isl97672a features extensiv e protection functions that flag whenever a fault occurs. the protections include string-open and short-circuit detections, ovp, otp, and an optional output short-circuit prot ection with a fault disconnect switch. the isl97672a is offered in a compact 20 ld qfn 3x4 package and can operate in ambient temperatures of -40c to +85c. features ?6 x 50ma channels ? 4.5v to 26.5v input ? 45v output max ? adaptive boost switching architecture ? direct pwm dimming with dimming linearity of 0.007%~100% at 200hz or 0.8%~100% <20khz ? adjustable 200khz to 1.4mhz switching frequency ? dynamic headroom control ? fault protections with latched flag indication -string open/short circuit -ovp -otp - optional output short-circuit fault protection switch ? current matching 0.7% ? 20 ld 3x4 qfn package applications ? notebook displays led backlighting ? lcd monitor led backlighting ? multi-function printer scanning light source typical application circuit v in = 4.5v~26.5v pwm comp vin fault ovp rset v out = 45v*, 6 x 50ma vdc /flag ch0 ch3 ch2 ch4 ch5 fsw 2 4 6 5 17 8 15 14 13 12 11 10 16 1 18 lx 20 pgnd 19 agnd 9 isl97672a ch1 en 3 * v in > 12v figure 1. isl97672a typical application diagram q1 optional may 2, 2011 fn7710.2
isl97672a 2 fn7710.2 may 2, 2011 block diagram pin configuration isl97672a (20 ld 3x4 qfn) top view figure 2. isl97672a block diagram ordering information part number (notes 1, 2, 3) part marking package (pb-free) pkg. dwg. # isl97672airz 672a 20 ld 3x4 qfn l20.3x4 ISL97672AIRZ-EVAL evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tech brief tb347 for details on reel specifications. 2. these intersil pb-free plastic pack aged products employ special pb- free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-fr ee products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl97672a . for more information on msl, please see tech brief tb363 . lx pgnd comp rset nc fsw agnd ch0 fault vin en vdc pwm /flag ovp ch5 ch4 ch3 ch2 ch1 1 2 3 4 5 6 16 15 14 13 12 11 20 19 18 17 78910
isl97672a 3 fn7710.2 may 2, 2011 pin descriptions (i = input, o = output, s = supply) pin name pin # type description fault 1 o fault disconnect switch. vin 2 s input voltage for device and led power. en 3 i the device needs 4ms for initial power-up enable. it will be disabled if it is not biased for longer than 28ms. vdc 4 s de-couple capacitor for internally generated supply rail. pwm 5 i pwm brightness control pin. /flag 6 o /flag is latched low under any fault condition and resets after input power is recycled or part is re-enabled. this pin is an open drain that needs pull-up. nc 7 i no connect. fsw 8 i boost switching frequency set pin by connecting a resi stor. see ?switching frequency? on page 10 for resistor calculation. agnd 9 s analog ground for precision circuits. ch0, ch1 ch2, ch3 ch4, ch5 10, 11, 12, 13, 14, 15 i input 0, input 1, input 2, input 3, input 4, input 5 to current source, fb, and monitoring. ovp 16 i overvoltage protection input. rset 17 i resistor connection for setting led current (see equation 1 for calculating the iled peak). comp 18 o boost compensation pin. pgnd 19 s power ground (lx power return). lx 20 o input to boost switch.
isl97672a 4 fn7710.2 may 2, 2011 absolute maximum ratings (ta = +25c) thermal information vin, en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 28v fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vin - 8.5v to vin + 0.3v vdc, comp, rset, pwm, ovp, fsw . . . . . . . . . . . . . . . . . . . . . -0.3v to 5.5v ch0 - ch5, lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 45v pgnd, agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v note: voltage ratings are with respect to agnd pin. esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 3kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 300v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kv thermal resistance (typical) ja (c/w) jc (c/w) 20 ld qfn package (notes 4, 5, 7) . . . . . . 40 2.5 thermal characterization (typical) psi jt (c/w) 20 ld qfn package (note 6) . . . . . . . . . . . . . . . . . . . . . 1 maximum continuous junction temperature . . . . . . . . . . . . . . . . .+125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb347 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. psi jt is the junction-to-top thermal resistance. if the package top te mperature can be measured, with this rating then the die junct ion temperature can be estimated more accurately than the ja and jc thermal resistance ratings. 7. refer to jesd51-7 high effective thermal conducti vity board layout for proper via and plane designs. electrical specifications all specifications are tested at t a = +25c, v in = 12v, en = 5v, r set = 20.1k , unless otherwise noted. parameter description condition min (note 8) typ max (note 8) unit general v in (note 9) backlight supply voltage t c = <+60c t a = +25c 4.5 26.5 v ivin vin current en = 5v 5 ma ivin_stby vin shutdown current t a = +25c 5 a v out output voltage 4.5v < v in 26v, f sw = 600khz 45 v 8.55v < v in 26v, f sw = 1.2mhz 45 v 4.5v < v in 8.55v, f sw =1.2mhz v in /0.19 v v uvlo undervoltage lock-out threshold 2.1 2.6 v v uvlo_hys undervoltage lock-out hysteresis 200 mv enable and pwm generator v il guaranteed range for pwm input low voltage 0.8 v v ih guaranteed range for pwm input high voltage 1.5 vdd v fpwm pwm input frequency range 200 30,000 hz t on minimum on time 250 350 ns
isl97672a 5 fn7710.2 may 2, 2011 regulator vdc ldo output voltage v in > 6v 4.55 4.8 5 v ivdc_stby standby current en = 0v 5 a vldo vdc ldo droop voltage v in > 5.5v, 20ma 20 200 mv en low guaranteed range for en input low voltage 0.5 v en hi guaranteed range for en input high voltage 1.8 v t enlow en low time before shut-down 30.5 ms boost sw ilimit boost fet current limit 1.5 2.0 2.7 a r ds(on) internal boost switch on-resistance t a = +25c 235 300 m ? ss soft-start 100% led duty cycle 7 ms eff_peak peak efficiency v in = 12v, 72 leds, 20ma each, l = 10h with dcr 101m ? , t a = +25c 92.9 % v in = 12v, 60 leds, 20ma each, l = 10h with dcr 101m ? , t a = +25c 90.8 % i out / v in line regulation 0.1 % d max boost maximum duty cycle f sw = 600khz 90 % f sw = 1.2mhz 81 % d min boost minimum duty cycle f sw = 600khz 9.5 % f sw = 1.2mhz 17 % f s minimum switching frequency r fsw = 200k ? 175 200 235 khz f s maximum switching frequency r fsw = 33k ? 1.312 1.50 1.69 mhz i lx_leakage lx leakage current lx = 45v, en = 0 10 a current sources i match channel-to-channel current matching r set =20.1k ? (i out = 20ma) 0.7 1.0 % i acc current accuracy -1.5 +1.5 % v headroom dominant channel current source headroom at iin pin i led = 20ma t a = +25c 500 mv v rset voltage at rset pin r set = 20.1k ? 1.2 1.22 1.24 v i ledmax maximum led current per channel v in = 12v, v out = 45v, f sw = 1.2mhz, t a = +25c 50 ma fault detection vsc short circuit threshold p wm dimming = 100% 7.5 8.2 v temp_shtdwn temperature shutdown threshold 150 c temp_hyst temperature shutdown hysteresis 23 c vovplo overvoltage limit on ovp pin 1.19 1.25 v flag_on fault flag when fault occurs, i pullup= 4ma 0.4 v electrical specifications all specifications are tested at t a = +25c, v in = 12v, en = 5v, r set = 20.1k , unless otherwise noted. parameter description condition min (note 8) typ max (note 8) unit
isl97672a 6 fn7710.2 may 2, 2011 fault pin i fault fault pull-down current v in = 12v 12 21 30 a v fault fault clamp voltage with respect to v in v in = 12, v in - v fault 678.3v lxstart_thres lx start-up threshold 0.9 1.2 v ilx startup lx start-up current vdc = 5.0v 1 3.5 5 ma notes: 8. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. 9. at maximum v in of 26.5v, minimum v out is 28v. minimum v out can be lower at lower v in . electrical specifications all specifications are tested at t a = +25c, v in = 12v, en = 5v, r set = 20.1k , unless otherwise noted. parameter description condition min (note 8) typ max (note 8) unit typical performance curves figure 3. efficiency vs up to 20ma led current (100% led duty cycle) vs v in figure 4. efficiency vs up to 30ma led current (100% led duty cycle) vs v in figure 5. efficiency vs v in vs switching frequency at 20ma (100% led duty cycle) figure 6. efficiency vs v in vs switching frequency at 30ma (100% led duty cycle) 100 70 80 90 50 30 40 60 0 10 20 0 5 10 15 20 25 efficiency (%) i led(ma) 5v in 12v in 24v in 100 70 80 90 50 30 40 60 0 10 20 0 5 10 15 20 25 efficiency (%) i led(ma) 30 35 6p10s_30ma/channel 5v in 12v in 24v in 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 1.2mhz 580k efficiency (%) v in 0 5 10 15 20 25 efficiency (%) v in 30 1.2mhz 0 20 40 60 80 100 580k
isl97672a 7 fn7710.2 may 2, 2011 figure 7. efficiency vs v in vs temperature at 20ma (100% led duty cycle) figure 8. channel-to-channel current matching figure 9. current linearity vs low level pwm dimming duty cycle vs v in figure 10. v headroom vs v in at 20ma figure 11. v out ripple voltage, v in = 12v, 6p12s at 20ma/channel figure 12. in-rush and led current at v in = 6v for 6p12s at 20ma/channel typical performance curves (continued) 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 +25c -40c 0c +85c efficiency (%) v in 0.40 0.10 0.20 0.30 -0.10 -0.20 0.00 012345 current matching (%) channel 6 -0.30 -0.40 7 21 v in 12 v in 4.5 v in 0 0.2 0.4 0.6 0.8 1.0 1.2 01 4 dc 23 56 current 4.5 v in 12 v in 0.40 0.45 0.50 0.55 0.60 0 5 10 15 20 25 30 v headroom (v) -40c 0c +25c v in (v) 2.00s/div v o = 50mv/div v in = 6v, 6p12s v o = 20v/div 2.00s/div i_v in = 1a/div iled = 20ma/div en
isl97672a 8 fn7710.2 may 2, 2011 figure 13. in-rush and led current at v in = 12v for 6p12s at 20ma/channel figure 14. line regulation with v in change from 6v to 26v, v in = 12v, 6p12s at 20ma/channel figure 15. line regulation with v in change from 26v to 6v for 6p12s at 20ma/channel figure 16. load regulation with i led change from 0% to 100% pwm dimming, v in =12v, 6p12s at 20ma/channel figure 17. load regulation with i led change from 100% to 0% pwm dimming, v in =12v, 6p12s at 20ma/channel figure 18. isl97672a shuts down and stops switching ~30ms after en goes low typical performance curves (continued) v in = 12v, 6p12s v o = 20v/div 2.00s/div i_v in = 1a/div iled = 20ma/div en 6p12s, 20ma/ch v in = 10v/div 10.0ms/div i_v in = 1a/div iled = 20ma/div en 6p12s, 20ma/ch v in = 10v/div 10.0ms/div i_v in = 1a/div iled = 20ma/div en 6p12s, 20ma/ch v o = 1v/div 10.0ms/div iled = 20ma/div 6p12s, 20ma/ch v o = 1v/div 10.0ms/div iled = 20ma/div 6p12s, 20ma/ch v o = 10v/div 20.0ms/div i_v in = 1a/div iled = 20ma/div en
isl97672a 9 fn7710.2 may 2, 2011 theory of operation pwm boost converter the current mode pwm boost converter produces the minimal voltage needed to enable the led stack with the highest forward voltage drop to run at the programmed current. the isl97672a employs current mode control boost architecture that has a fast current sense loop and a slow voltage feedback loop. such architecture achieves a fast transient response that is essential for notebook backlight applications in which drained batteries can be instantly changed to an ac/dc adapter without noticeable visual disturbance. th e number of leds that can be driven by isl97672a depends on the type of led chosen in the application. the isl97672a is capable of boosting up to 45v and typically driving 13 leds in series for each of the 8 channels, enabling a total of 104 pieces of the 3.2v/20ma type of leds. enable the enable pin is used to enable the device. if there is no signal for longer than 28ms, the device enters shutdown. the enable pin should not float. if it does, a 10k or higher pull-down resistor should be added. ovp and v out the overvoltage protection (ovp) pi n has a function of setting the overvoltage trip level as well as limiting the v out regulation range. the isl97672a ovp threshold is set by r upper and r lower such that: v out _ovp = 1.21v * (r upper + r lower )/r lower and v out can only regulate between 61% and 100% of the v out _ovp such that: allowable v out = 61% to 100% of v out _ovp if, for example, 10 leds are used with the worst-case v out of 35v. if r 1 and r 2 are chosen such that the ovp level is set at 40v, then v out is allowed to operate between 24.4v and 40v. if the v out requirement is changed to an a pplication of six leds of 21v, then the ovp level must be reduced. users should follow the v out = (61% ~100%) ovp level requirement; otherwise, the headroom control will be disturbe d such that the channel voltage can be much higher than expected. this can sometimes prevent the driver from operating properly. the ratio of the ovp capacitors should be the inverse of the ovp resistors. for example, if r upper /r lower = 33/1, then c upper /c lower = 1/33 with c upper = 100pf and c lower =3.3nf. current matching and current accuracy each channel of the led current is regulated by the current source circuit, as shown in figure 21. the led peak current is set by translating the r set current to the output, with a scaling factor of 401.8/r set . the source terminals of the current source mosfets ar e designed to run at 500mv to optimize power loss versus accu racy requirements. the sources of errors of the channel-to-channel current matching come from the op amp?s offset, internal layout, and reference, and these parameters are optimized for current matching and absolute current accuracy. the absolute accuracy is also determined by the external r set . a 1% tolerance resistor should be used. figure 19. minimum dimming linearity at 200hz figure 20. minimum dimming linearity at 20khz typical performance curves (continued) 30 25 20 15 10 6 7 8 9 1011121314 pwm dimming duty cycle (%) i led (ma) i led = 20ma f pwm = 200hz no ch caps i led = 20ma f pwm = 20khz i led (ma) 0 0.4 1.2 2.0 2.8 3.2 3.6 4.4 4.8 0.8 1.6 2.4 4.0 5.2 1.2 1.0 0.8 0.6 0.4 0.2 0.0 pwm dimming duty cycle (%) figure 21. simplified current source circuit ref + - + - pwm dimming rset + ref + - + - rset -
isl97672a 10 fn7710.2 may 2, 2011 dynamic headroom control the isl97672a features a pr oprietary dynamic headroom control circuit that detects the highest forward voltage string or effectively the lowest voltage from any of the ch0 through ch5 pins. when this lowest channe l voltage is lower than the short-circuit threshold, v sc , this voltage is used as the feedback signal for the boost regulator. the boost adjusts the output to the correct level such that the lowest channel pin is at the target headroom voltage. since all led stacks are connected to the same output voltage, the other channel pins will have a higher voltage, but the regulated current source circuit on each channel ensures that each channel has the same current. the output voltage regulates cycle by cycle, and it is always referenced to the highest forward voltage string in the architecture. dimming controls the isl97672a allows two ways of controlling the led current, and therefore, the brightness. they are: 1. dc current adjustment 2. pwm chopping of the led current defined in step 1. maximum dc current setting the initial brightness should be set by choosing an appropriate value for r set . this should be chosen to fix the maximum possible led current: for example, if the maximum required led current (i led(max) ) is 20ma, rearranging equation 1 yields equation 2: pwm current control the isl97672a employs direct pwm dimming such that the output pwm dimming follows directly with the input pwm signal without modifying the input frequency. the average led current of each channel can be calculated as shown in equation 3: switching frequency the boost switching frequency can be adjusted by a resistor as shown in equation 4: where f sw is the desirable boost sw itching frequency, and r fsw is the setting resistor. 5v low dropout regulator a 5v low dropout (ldo) regulator is present at the vdc pin to develop the necessary low-voltage supply, which is used by the chip?s internal control circuitry. because vdc is an ldo pin, it requires a bypass capacitor of 1f or more for the regulation. the vdc pin can be used as a coarse reference as long as it is sourcing only a few milliamps. power-up sequencing, soft-start, and fault management to reduce in-rush current as various bulk capacitors charge up, the isl97672a includes circuits to manage input current draw during normal start-up. the isl97672a also detects several external fault conditions and ac ts to limit fault energy and prevent continued start-up while detected faults exist. optionally, an external high-side pfet can be fitted in series with vin. the isl97672a turns this fault protection pfet off in the event of a short fault to ground in the boost converter. this action prevents damage to the system's main power supply in such an overload condition. in-rush control and soft-start the isl97672a has separate, built-in, independent in-rush control and soft-start functions. the in-rush control function is built around the short-circuit protection fet and is only available in applications that include this device. at start-up, the fault protection fet is turned on slowly due to a 30a pull-down current output from the fault pin. this discharges the fault fet's gate-source capacitance, turning on the fet in a controlled fashion. as this happens, the output capacitor is charged slowly through the low-current fet befo re it becomes fully enhanced. this results in a low in-rush current. this current can be further reduced by adding a capacitor (i n the 1nf to 5nf range) across the gate source terminals of the fet. once the chip detects that the fault protection fet is turned on fully, it assumes that in-rush is co mplete. at this point, the boost regulator begins to switch, and the current in the inductor ramps up. the current in the boost power switch is monitored, and switching is terminated in any cycle in which the current exceeds the current limit. the isl97672a in cludes a soft-start feature in which this current limit starts at a low value (275ma). this value is stepped up to the final 2.2a current limit in seven additional steps of 275ma each. these step s happen over at least 8ms and are extended at low led pwm frequencies if the led duty cycle is low. this extension allows the output capacitor to charge to the required value at a low current limit and prevents high input current for systems that have only a low to medium output current requirement. for systems with no master fault protection fet, the in-rush current flows towards c out when v in is applied. the in-rush current is determined by the ramp rate of v in and the values of c out and l. fault protection and monitoring the isl97672a features extensive protection functions to cover all perceivable failure conditions. the /flag pin is a latched open-drain output that monitors string open, led short, v out short, and overvoltage and over-temperature conditions. this pin resets only when input power is recycled or the part is re-enabled. the failure mode of an led can be either an open circuit or a short. the behavior of an open -circuited led can additionally take the form of either infinite resistance or, for some leds, a zener diode, which is integrated into the device in parallel with the now-opened led. i ledmax 401.8 r set --------------- = (eq. 1) r set 401.8 0.02 ? 20.1k == (eq. 2) i led ave () i led pwm = (eq. 3) f sw 5 10 10 () r fsw ----------------------- - = (eq. 4)
isl97672a 11 fn7710.2 may 2, 2011 for basic leds (which do not ha ve built-in zener diodes), an open-circuit failure of an led results only in the loss of one channel of leds, without affecting other channels. similarly, a short-circuit condition on a channel that results in that channel being turned off does not affect other channels unless a similar fault is occurring. due to the lag in boost response to any load change at its output, certain transient events (such as led current steps or significant step changes in led duty cycle) can transiently look like led fault modes. the isl97672a uses feedback from the leds to determine when it is in a stable operating region and prevents apparent faults during these tran sient events from allowing any of the led stacks to fault out. see table 1 for details. a fault condition that results in an input current that exceeds the device?s electrical limits will result in a shutdown of all output channels. short-circuit protection (scp) the short-circuit detection circuit monitors the voltage on each channel and disables faulty channels that are above approximately 7.5v (this action is described in table 1 on page 12). open-circuit protection (ocp) when one of the leds becomes an open circuit, it can behave as either an infinite resistance or as a gradually increasing finite resistance. the isl97672a monitors the current in each channel such that any string that reaches the intended output current is considered ?good.? should the cu rrent subsequently fall below the target, the channel is considered an ?open circuit.? furthermore, should the boost output of the isl97672a reach the ovp limit, or should the lower over-temperature threshold be reached, all channels that are not good are immediately considered to be open circuit. detection of an open circuit channel results in a time-out before the affected channel is disabled. this time-out is sped up when the device is above the lower over-temperature threshold, in an attempt to prevent the upper over-temperature trip point from being reached. some users employ special type s of leds that have a zener diode structure in parallel with the led. this configuration provides esd enhancement and enables open-circuit operation. when this type of led is open circuited, the effect is as if the led forward voltage has increased but the lighting level has not increased. any affected string will not be disabled, unless the failure results in the boost ovp limit being reached, which allows all other leds in the string to rema in functional. in this case, care should be taken that the boost ovp limit and scp limit are set properly, to ensure that multiple failures on one string do not cause all other good channels to fault out. this condition could arise if the increased forward voltage of the faulty channel makes all other channels look as if they have led shorts. see table 1 for details of responses to fault conditions. overvoltage protection (ovp) the integrated ovp circuit monitors the output voltage and keeps the voltage at a safe level. the ovp threshold is set as shown in equation 5: the resistors should be large, to minimize power loss. for example, a 1m r upper and a 30k r lower sets ovp to 41.2v. large ovp resistors also allow c out to discharge slowly during the pwm off time. parallel capacitors should also be placed across the ovp resistors such that r upper /r lower = c lower /c upper . using a c upper value of at least 30pf is recommended. these capacitors reduce the ac impedance of the ovp node, which is important when using high-value resistors. undervoltage lock-out if the input voltage falls below the uvlo level of 2.45v, the device stops switching and is reset. op eration restarts only when v in returns to the normal operating range. input overcurrent protection during a normal switching oper ation, the current through the internal boost power fet is monitored. if the current exceeds the current limit, the internal switch is turned off. monitoring occurs on a cycle-by-cycle basis in a self-protecting way. additionally, the isl97672a monitors the voltage at the lx and ovp pins. at start-up, the lx pins inject a fixed current into the output capacitor. the device does not start unless the voltage at lx exceeds 1.2v. the ovp pin is also monitored such that if it rises above and subsequently falls below 20% of the target ovp level, the input protection fet is also switched off. over-temperature protection (otp) the isl97672a includes two over -temperature thresholds. the lower threshold is set to +130c. when this threshold is reached, any channel that is outputting curr ent at a level significantly below the regulation target is treated as ?open circuit? and is disabled after a time-out period. this time-out pe riod is reduced to 800s when it is above the lower threshold. th e lower threshold isolates and disables bad channels before they cause enough power dissipation (as a result of other channels havi ng large voltages across them) to hit the upper temperature threshold. the upper threshold is set to +150c . each time this threshold is reached, the boost stops switching, and the output current sources switch off. once the devi ce has cooled to approximately +100c, the device restarts, with the dc led current level reduced to 75% of the initial setting. if dissipation persists, subsequent hitting of the limit causes identical behavior, with the current reduced in steps to 50% and finally 25%. unless disabled via the en pin, the device stays in an active state throughout. for complete details of fault protection conditions, see figure 22 and table 1. ovp 1.21v r upper r lower + () r lower ? = (eq. 5)
isl97672a 12 fn7710.2 may 2, 2011 table 1. protections table case failure mode detection mode failed channel action good channel action v out regulated by 1ch0 short circuit upper over-temperature protection limit (otp) not triggered, and ch0<7.5v ch0 on and burns power. ch1 throug h ch5 normal highest vf of ch1 through ch5 2 ch0 short circuit upper otp triggered, but vch0 < 7.5v all channels go off until chip cools, and then come back on with current reduced to 76%. subsequent otp triggers further reduce i out . same as ch0 highest vf of ch1 through ch5 3 ch0 short circuit upper otp not triggered, but ch0 > 7.5v ch1 disabled after six pwm cycle time-outs. ch1 through ch5 normal highest vf of ch1 through ch5 4 ch0 open circuit with infinite resistance upper otp not triggered, and ch0 < 7.5v v out ramps to ovp. ch1 times out after six pwm cycles and switches off. v out drops to normal level. ch1 through ch5 normal highest vf of ch1 through ch5 5ch0 led open circuit but has paralleled zener upper otp not triggered, and ch0 < 7.5v ch1 remains on and has highest vf; thus, v out increases. ch1 through ch5 on, q1 through q5 burn power vf of ch0 figure 22. simplified fault protections q5 vsc ch5 vset pwm/oc0/sc0 ref fet driver lx imax ilimit driver fault ovp vin t2 otp thrm shdn q0 vsc ch0 vout vset pwm/oc5/sc5 temp sensor logic lx t1 otp thrm shdn o/p short fault detect logic pwm generator fault flag /flag
isl97672a 13 fn7710.2 may 2, 2011 component selection according to the inductor voltage-second balance principle, the change of inductor current duri ng the switching regulator on time is equal to the change of inductor current during the switching regulator off time. as shown in equations 6 and 7, since the voltage across an inductor is: and i l @ on = i l @ off, therefore: where d is the switching duty cycle defined by the turn-on time over the switching period. v d is a schottky diode forward voltage that can be neglected for approximation. rearranging the terms without accounting for v d gives the boost ratio and duty cycle, respectively, as shown in equations 8 and 9: input capacitor switching regulators require input capacitors to deliver peak charging current and to reduce the impedance of the input supply. the capacitors reduce interaction between the regulator and input supply, thus improvin g system stability. the high switching frequency of the loop causes almost all ripple current to flow into the input capacitor, which must be rated accordingly. a capacitor with low internal seri es resistance should be chosen to minimize heating effects and to improve system efficiency. the x5r and x7r ceramic capacitors offer small size and a lower value for temperature and voltage coefficient compared to other ceramic capacitors. in boost mode, input current flows continuously into the inductor, with an ac ripple component proportional to the rate of inductor charging only. in this mode, smaller-value input capacitors may be used. an input capacitor of at least 10f is recommended. ensure that the voltage rating of the input capacitor is able to handle the full supply range. inductor inductor selection should be based on its maximum current (i sat ) characteristics, power dissipati on (dcr), emi susceptibility (shielded vs unshielded), and size. inductor type and value influence many key parameters, including ripple current, current limit, efficiency, transient performance, and stability. inductor maximum current capability must be adequate to handle the peak current in the worst-case condition. if an inductor core with too low a current rating is chosen, saturation in the core will cause the effectiv e inductor value to fall, leading to an increase in peak-to-average current level, poor efficiency, and overheating in the core. the series resistance, dcr, within the inductor causes conduction loss and heat dissipation. a shielded inductor is usually more suitable for emi-susceptible applications such as led backlighting. the peak current can be derived from the voltage across the inductor during the off period, as shown in equation 10: the value of 85% is an average term for the efficiency approximation. the first term is average current that is inversely proportional to the input voltage. the second term is inductor 6ch0 led open circuit but has paralleled zener upper otp triggered, but ch0 < 7.5v all channels go off until chip cools, and then come back on with current reduced to 76%. subsequent otp triggers further reduce i out . same as ch0 vf of ch0 7ch0 led open circuit but has paralleled zener upper otp not triggered, but chx > 7.5v ch0 remains on and has highest vf; thus, v out increases. v out increases, then ch-x switches off after six pwm cycles. this is an unwanted shut off and can be prevented by setting ovp at an appropriate level. vf of ch0 8 channel-to-channel vf too high lower otp triggered, but chx < 7.5v any channel below the target current faults out after six pwm cycles. remaining channels are driv en with normal current. highest vf of ch0 through ch5 9 channel-to-channel vf too high upper otp triggered, but chx < 7.5v all channels go off until chip cools and then come back on with current reduced to 76%. subsequent otp triggers further reduce i out . highest vf of ch0 through ch5 10 output led stack voltage too high v out > vovp any channel that is below the targ et current times out after six pwm cycles, and v out returns to normal regulation voltage required for other channels. highest vf of ch0 through ch5 11 v out /lx shorted to gnd at start-up, or v out shorted in operation lx current and timing monitored. ovp pins monitored for excursions below 20% of ovp threshold. chip is permanently shut down 31ms after power-up if v out /lx is shorted to gnd. table 1. protections table (continued) case failure mode detection mode failed channel action good channel action v out regulated by v l l i l t ? = (eq. 6) v ( i 0 ) l ? dt s v o v d v i ? ? () = l1 ( d ) t s ? ? ? (eq. 7) v o v i 11d ? () ? = ? (eq. 8) dv o ( v i ) v o ? ? = (eq. 9) il peak v o ( i o ) 85% ( v i ) 12v i v o ( v i ) l ( v o f s ) ? ? [] ? + ? = (eq. 10)
isl97672a 14 fn7710.2 may 2, 2011 current change that is inversely proportional to l and f s . as a result, for a given switching frequency and minimum input voltage at which the system operates, the inductor i sat must be chosen carefully. usually, at a given inductor size, the larger the inductance, the higher the series resistance because of the extra winding of the coil. thus, the higher the inductance, the lower the peak current capability. the is l97672a current limit may also have to be considered. output capacitors the output capacitor smooths the output voltage and supplies load current directly during th e conduction phase of the power switch. output ripple voltage consists of the discharge of the output capacitor for i lpeak during fet on and the voltage drop due to flow through the esr of the output capacitor. the ripple voltage can be shown as equation 11: the conservation of charge prin ciple shown in equation 9 also indicates that, during the boost switch off period, the output capacitor is charged with the inductor ripple current, minus a relatively small output current in boost topology. as a result, the user must select an output capacitor with low esr and adequate input ripple current capability. output ripple the value of v co can be reduced by increasing c o or f s , or by using small esr capacitors. in general, ceramic capacitors are the best choice for output capacitors in small- to medium-sized lcd backlight applications, due to their cost, form factor, and low esr. a larger output capacitor also eases driver response during the pwm dimming off period, due to the longer sample and hold effect of the output drooping. the driver does not need to boost harder in the next on period that minimizes transient current. the output capacitor is also needed for compensation, and in general, 2x4.7f/50v ceramic capacitors are suitable for notebook display backlight applications. schottky diode a high-speed rectifier diode is necessary to prevent excessive voltage overshoot, especially in the boost configuration. schottky diodes are the preferred choice because of their low forward voltage and reverse leakage curr ent, which minimize losses. although the schottky diode turn s on only during the boost switch off period, it carries the same peak current as the inductor, and therefore, a suitable current-rated schottky diode must be used. applications high-current applications each channel of the isl97672a can support up to 30ma. for applications that need higher current, multiple channels can be grouped to achieve the desired current (figure 23). for example, the cathode of the last led can be connected to ch0 through ch2; this configuration can be tr eated as a single string with 90ma current driving capability. low-voltage operations the isl97672a vin pin can be separately biased from the led power input to allow low-voltage operation. for systems that have only a single supply, v out can be tied to the driver vin pin to allow initial start-up (figure 24). the circuit works as follows: when the input voltage is available and the device is not enabled, v out follows v in with a schottky diode voltage drop. the v out boot- strapped to the vin pin allows initial start-up, once the part is enabled. once the driver starts up with v out regulating to the target, the vin pin voltage also increases. as long as v out does not exceed 26.5v and the extra power loss on v in is acceptable, this configuration can be used for input voltage as low as 3.0v. the fault protection fet feature cannot be used in this configuration. for systems that have dual supplies, the vin pin can be biased from 5v to 12v, while input voltage can be as low as 2.7v (figure 25). in this configuration, vbias must be greater than or equal to vin to use the fault fet. v co i ( o c o df s ) i ( o esr () + ? ? = (eq. 11) figure 23. grouping multiple channels for high current applications ch0 ch1 ch2 v out figure 24. single supply 3.0v operation v in = 3.0v~21v pwm comp vin ovp rset vdc /flag ch0 ch3 ch2 ch4 ch5 fsw 2 4 6 5 17 8 15 14 13 12 11 10 16 18 lx 20 pgnd 19 agnd 9 isl97672a ch1 en 3 26.5v, 6 x 50ma * fault 1 *vin > 12v
isl97672a 15 fn7710.2 may 2, 2011 compensation the isl97672a has two main elements in the system: the current mode boost regulator, and the op amp-based, multi-channel current sources. the isl97672a incorporates a transconductance amplifier in its feedback path to allow the user better regulation and some level of adjustment on the transient response. the isl97672a us es current mode control architecture, which has a fast current sense loop and a slow voltage feedback loop. the fast current feedback loop does not require any compensation, but fo r stable operation, the slow voltage loop must be compensated. the compensation network is a series rc, cc1 network from comp pin to ground, with an optional cc2 capacitor connected to the comp pin. the rc sets the high-frequency integrator gain for fast transient response, and the cc1 sets the integrator zero to ensure loop stability. for most applications, rc is in the range of 15k ? , and cc1 is in the range of 2.2nf. depending upon the pcb layout, for stability, a cc2 in the range of 47pf may be needed to create a pole to cancel the output capacitor esr?s zero effect. figure 25. dual supply 2.7v operation v in = 2.7~26.5v 45v, 6 x 50ma * *vin > 12v pwm comp vin ovp rset vdc /flag ch0 ch3 ch2 ch4 ch5 fsw 2 4 6 5 17 8 15 14 13 12 11 10 16 18 lx 20 pgnd 19 agnd 9 isl97672a ch1 en 3 vbias = 5v~12v fault 1 q1(optional)
isl97672a 16 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7710.2 may 2, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl97672a to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change april 13, 2011 fn7710.2 pg. 5, electrical specifications table: for v rset parameter, changed units from mv to v. march 24, 2011 fn7710.1 initial release to web
isl97672a 17 fn7710.2 may 2, 2011 package outline drawing l20.3x4 20 lead quad flat no-lead plastic package rev 1, 3/10 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 0.10 m c a b mc 0.05 0.15 0.08 c 0.10 c a b c c 4.00 3.00 20x 0.400.10 2.65 1.65 0.25 0.50 (2.80) (1.65) +0.10 -0.15 +0.10 -0.15 +0.05 -0.07 20x a a 4 (4x) seating plane 0.9 0.10 5 0.2 ref 0.05 max. see detail "x" 0.00 min. (c 0.40) 1 20 17 16 11 6 10 7 (3.80) (2.65) (20 x 0.25) (20 x 0.60) (16 x 0.50) 16x view "a-a" pin 1 index area pin 1 index area 6 6

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